Axera AX8860 vs DGX Spark: Sipeed's MaixStation Claims, Checked

On 13 October, at the Shanghai industrial expo, Chinese chipmaker Axera announced the AX8860, a 6 nm edge AI chip with a 16-core Arm CPU, a 256 TOPS NPU with native FP4, and up to 128 GB of LPDDR5X on a 256-bit bus at 273 GB/s. The same day, Sipeed, a Shenzhen maker of small Linux boards, opened reservations for the MaixStation, a 363 cm³ box built around it, and told the world it "beats DGX Spark" on Qwen 27B: 25% faster prefill, 30% faster decode, at 40 W and about half the price. Wccftech ran the headline, and the line went around.

We run two GB10 boxes, the chip inside every DGX Spark, so this one is ours to check. The spec sheet is the GB10's spec sheet, the claims pass a physics check at the low end and fail it at the high end, and nothing exists to buy until a Kickstarter at the end of the year.

The same memory, to the digit

The memory row is the whole story. Axera chose the exact configuration NVIDIA chose for the GB10: a 256-bit LPDDR5X bus at 8,533 MT/s, which is where 273 GB/s comes from on both. That is a sensible decision, since LPDDR5X on a wide bus is the cheapest way to put 128 GB next to an accelerator, and it means the two parts have an identical ceiling on the operation that decides single-user LLM speed.

Everything else is weaker on paper. The CPU is sixteen Cortex-A55s, a 2017 efficiency core that phones use as the small cluster; the GB10 carries twenty cores of which ten are Arm's largest. The NPU's 256 dense TOPS is half the GB10's dense figure. Sipeed's answer to that is on its own page: NVIDIA's "1,000 TOPS" is sparse and real models cannot use it, dense is 500 on paper, and "on real models Spark puts only a small slice of it to work". That last part is true, and it is why the prefill claim is not absurd.

What Sipeed actually measured

The comparison lives on the MaixStation page as animated bars, with "MTP disabled" on both sides and a note that "AX8860P is still being tuned. Bars show today's low to high; even the low end beats DGX Spark." The values behind the animation:

Two things before judging the numbers. First, the DGX Spark baseline is fair. Independent runs of Qwen3.8-27B on a DGX Spark without speculative decoding land at 11.5 tok/s in vLLM with NVFP4 and 11.6 in llama.cpp, with prefill between 840 and 1,900 depending on the engine; Sipeed's 13 and 1,300 sit inside that spread, if anything slightly generous to NVIDIA. Second, the headline percentages are the top of Sipeed's own range. The low end is 8% faster prefill and 15% faster decode on the dense model, and a dead tie on MoE decode. "25% and 30%" is what the bars say on a good day of tuning.

Sipeed also pre-empts the obvious objection, that people have seen a Spark do 50 tok/s on a 27B: "those runs use MTP or speculative decoding. This chart turns MTP off on both sides for a like-for-like baseline. Turn it on, and MaixStation gets a similar speedup." We measured exactly that speedup on the same model: 2.2 to 2.4× on a 5090, and on a DGX Spark the SGLang-plus-DSpark path reports 34 to 38. A like-for-like baseline is the right comparison. Whether the AX8860's NPU runs a draft head as well as a GPU does is a separate question nobody has answered.

The physics check

Decode is a bandwidth problem. Every generated token reads every weight once, so tokens per second is at most bandwidth divided by model size, a rule we have leaned on since the two speeds of an LLM. Qwen3.8-27B in FP4 is about 16 GB on disk. On a 273 GB/s bus the ceiling is 273 ÷ 16, just over 17 tokens a second, before a single byte of KV cache, activations or overhead.

The low end is a real engineering claim: 88% of theoretical bandwidth is what a well-written kernel achieves on a GPU, and the GB10's stack sits at two thirds, so there is room. We measured the same gap on the other side of the fence: a 27B on an RTX 5090 reaches 61% of that card's bandwidth. Beating NVIDIA's software utilisation on NVIDIA-matched memory is possible.

The high end is not a claim about engineering. 17 tok/s on a 16 GB model is the bus running at 100%, with no DRAM refresh, no KV cache reads, no page misses and no attention. No shipping system reads memory at its theoretical peak during decode. If Sipeed's tuning reaches the top of its own bars, the model is smaller than 16 GB or the bus is faster than 273 GB/s. Either way, the honest version of "30% faster decode" is "we are chasing the last 12% of the bus that NVIDIA leaves on the table, and we have reached some of it".

Prefill is a compute problem, and there the claim is easier. A 27B dense model costs about 54 GFLOP per prompt token, so 1,600 tok/s is 86 TFLOPS, a third of the AX8860's 256 dense TOPS. The DGX Spark's 1,300 is 70 TFLOPS, a seventh of its 500 dense. Sipeed's point that NVIDIA's stack uses a small slice of the GB10's compute on these models is borne out by NVIDIA's own numbers, and a purpose-built NPU running at a third of its peak is not an outlandish thing to build.

What the page claims that we would want most

Sipeed's cluster ladder is the part aimed at readers of this site: one 32 GB node for Qwen3.8-27B, one 128 GB node for Qwen3.8-Flash-Next, two nodes over an MCIO cable for DeepSeek-V4-Flash, and a "MaixStation Pro" at 512 GB for DeepSeek-V4.1-Flash. Three weeks ago we worked out that V4.1 does not fit two GB10s and four do not help, because the GB10's prefill does not scale across boxes. A single box with 512 GB on one bus is the shape that would change that answer, and it is the one furthest from a product: no photo, no price, no date.

The cascading claim has a footnote worth reading. Axera's slide puts two chips at 512 TOPS and four at 1,024 with "about 80% efficiency", and the small print at the bottom says, in Chinese, based on laboratory simulation data. The 4-chip MaixBlade PCIe card exists as hardware in Sipeed's photographs; the scaling figure for it does not yet exist as a measurement.

DeepSeek-V4-Flash: two nodes, or one big one

Many of the people reading this run DeepSeek-V4-Flash on two GB10s over a 200 Gb cable, as we do. The model needs 155 GiB at native precision, so on either chip it is two 128 GB nodes or a single node with more memory. Sipeed's ladder offers both: V4-Flash on two nodes over MCIO, and the 512 GB "Pro" that would hold it on one bus.

Two nodes: the "slow" link is not the problem. MCIO 8i is PCIe 5.0 ×8, about 32 GB/s each way; the pair's direct 200 Gb RoCE cable is 25 GB/s. And we measured that the pair uses 1.3% of its fabric during decode and 7.4% during prefill, so bandwidth between the boxes was never the constraint. What limits tensor-parallel decode on the pair is allreduce latency, two synchronisations per layer per token. On a MaixStation that cost lands on sixteen Cortex-A55s and Axera's PCIe stack instead of a ConnectX-7 and NCCL, and there is no reason to expect it to be lower. Two MaixStations in tensor parallel are, on paper, a slower pair.

One 256 or 512 GB box: the shape that would win. A single node drops the allreduce entirely. V4-Flash reads roughly 8 to 10 GB per token at its 13B active parameters, so one 273 GB/s bus allows 27 to 34 forward passes a second where the pair manages 14.9, because the pair is latency-bound rather than bandwidth-bound. With DSpark accepting 5.94 tokens a step, the ceiling is near 160 to 200 tok/s on structured output against the pair's measured 88, and prefill at a third of 256 dense TOPS would be about 3,300 tok/s against the pair's 1,700 to 1,800. Both are ceilings, and both assume Axera's stack runs MoE routing and a draft head as well as vLLM does on a GPU.

Three things weigh against the paper. Sipeed's ladder also claims Qwen3.8-Flash-Next on one 128 GB node, and that checkpoint is 126 GiB resident, which did not fit one GB10 with 121 GB usable; that is a tighter quant, a smaller OS footprint, or an optimistic slide. The 512 GB Pro has no photo, no date and no price. And running MoE dispatch, speculative decoding and a million-token KV cache on a custom NPU is exactly the software that has never been shown at any model size.

So the conclusion for the dual-Spark crowd: if a single-box 256 GB MaixStation ships at the price its 128 GB sibling implies, it is the first hardware whose spec sheet beats the pair on V4-Flash, and it would do so by removing the interconnect rather than by being faster silicon. Whether the silicon and its software deliver that remains to be seen. Until it ships, two GB10s remain the only configuration anyone has measured.

What exists today

• The chip. Announced, shown on stage with modules and cards, not yet listed on Axera's own product pages. Radxa's preview of the same silicon says "up to 128 TOPS"; Sipeed and Axera say 256. Whether those are two bins of one chip or one chip described twice, nobody has said.
• The box. Reservations at $30, credited as $100 at purchase. Kickstarter "end of 2026". Prices given as "$1,xxx" and "$3,xxx".
• The software. Sipeed lists vLLM, SGLang, PyTorch, llama.cpp and Ollama. All of those are written for GPUs; running them on a custom NPU behind sixteen A55 cores means Axera's own backend doing the work and the frameworks providing the API surface. Axera's toolchain for its earlier chips, Pulsar2, compiles models offline into NPU graphs. How much of the vLLM feature list survives that, prefix caching, speculative decoding, concurrent requests, is the question that decides whether the bars on the page are the product.
• The measurements. Sipeed's, on hardware that is "still being tuned", with no methodology, no prompt lengths, no context sizes, and the top of each range sitting at a physical limit.

Bottom line

• Same bus, same ceiling. The AX8860 copies the GB10's memory configuration exactly, so single-stream decode can only ever be as fast as the GB10's could be. The contest is software utilisation, and NVIDIA's stack leaves a third on the table.
• The low end of Sipeed's claim is plausible, 8 to 15% faster on the dense model and a tie on MoE decode. The headline 25 and 30% are the top of the range, and the top of the decode range is the bus at 100%, which nothing ships at.
• Prefill is the stronger claim. A third of 256 dense TOPS beats a seventh of 500, and NVIDIA's own numbers show the GB10 running well under its compute peak on these models.
• Nothing is for sale. Kickstarter at year end, prices with x's in them, a chip two vendors describe with different TOPS, and scaling figures from a simulation.

If a MaixStation turns up on this desk, the first test is the one Sipeed invites: Qwen3.8-27B, FP4, MTP off, beside a GB10 with the same prompts, then MTP on, then the Serbian prose and the invoice. Until then, this is the most interesting spec sheet of the autumn and a set of bars on a web page.

Related reading

• GB10, DGX Spark, HP ZGX Nano, ASUS Ascent GX10: Eight Names for One 128 GB Box — the machine this one copies
• Prompt Processing vs Token Generation: the Two Speeds of an LLM — why decode is bandwidth and prefill is compute
• Qwen3.8-27B Is 2.3× Faster With One Flag — the speculative decoding both sides switched off
• Should You Upgrade to DeepSeek V4.1 Flash? We Tested It on Two DGX Sparks — why a 512 GB single box would matter
• RTX 5090 Prices: 3× Launch in the US, 2.4× in Europe, and Still Climbing — the price pressure a cheaper 128 GB box is aimed at